Electronic devices often employ multiple semiconductor components, e.g., several microchips. Some devices can be implemented in “multi-chip modules” that typically comprise a printed circuit board (PCB) substrate onto which a set of separate microchips is directly attached. Such multi-chip modules can increase circuit density and miniaturization, but they also can be bulky.
One method for reducing the size of multi-chip modules and thereby increasing their effective density is to stack the die or chips vertically. Conventional examples of this approach are the package-on-package (PoP) and package-in-package (PiP) configurations which can save space, e.g., on a PCB. These packages can be, for example, on the order of about 15 mm square, with a height of about 2 mm.
Some package designs place an interposer above a die. For example, U.S. Pat. No. 6,861,288 to Shim et al. discloses: “A method for fabricating a stacked semiconductor package includes providing a substrate and mounting a first semiconductor device on the substrate. An interposer is supported above the first semiconductor device opposite the substrate. The interposer is electrically connected to the substrate. A second semiconductor device is then mounted on the interposer.” See Abstract. However, this design can result in a package with an area much larger than the area of the packaged die.
In view of the above, improved semiconductor packages and packaging methods are needed.